Decoding this embedded PowerPc code snippet
I have this below code snippet from kernel source for PowerPc
#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
unsigned long ivor[3];
ivor[0] = mfspr(SPRN_IVOR32);
#define __stringify_1(x) #x
#define __stringify(x) __stringify_1(x)
#define mfspr(rn) ({unsigned long rval; \
asm volatile("mfspr %0," __stringify(rn) \
: "=r" (rval)); rval; })
Also, is this exercise above about emulating MSR bits in PowerPc?
Can anyone help me on what exactly we are doing here?
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The macro mfspr
generates an asm command mfspr
that reads the given special-purpose register into a register selected by the compiler, which is then assigned rval
, therefore, becomes the return value of the expression.
As the comment says SPRN_IVOR32
- this is Interrupt Vector Offset Register 32
whose content is thus loaded into ivor[0]
.
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