Rising_edge (clk) not synthesized
I am learning and programming VHDL for an FPGA to mimic the functionality of a 74HCT245. Below is my code.
I keep getting the instruction not synthesized as it doesn't matter in the NOT (clock-edge) state. VHDL-1242 ,
entity HCT541 is
port (Clk : in std_logic;
A : inout std_logic_vector(15 downto 0) := "1011101010111010";
BA : out std_logic_vector(15 downto 0);
n_OE, DIR : in std_logic;
M_D : inout std_logic_vector(15 downto 0) := "0000000000000001";
D : inout std_logic_vector(15 downto 0) := "1011101010111010";
BD : inout std_logic_vector(15 downto 0) := "1011101010111010");
end HCT541;
architecture df of HCT541 is
signal n_OE_1, n_OE_2 : std_logic := '0';
begin
process(Clk, n_OE, DIR)
begin
if ((BD = "ZZZZZZZZZZZZZZZZ" or D = "ZZZZZZZZZZZZZZZZ") and n_OE = '0') then
BD <= "0000000000000000";
D <= M_D;
end if;
M_D <= M_D + '1';
CLK1 : if(rising_edge(Clk)) then
if(n_OE_1 = '0' and n_OE_2 = '0') then
A <= A - '1';
BA <= A;
else
BA <= "ZZZZZZZZZZZZZZZZ";
end if;
if (n_OE = '0' and DIR = '1') then
D <= M_D;
BD <= D;
elsif (n_OE = '0' and DIR = '0') then
BD <= BD - '1';
D <= BD;
elsif (n_OE = '1') then
BD <= "ZZZZZZZZZZZZZZZZ";
D <= "ZZZZZZZZZZZZZZZZ";
end if;
end if CLK1;
end process;
end df;
any thoughts?
Is there something wrong with boost_edge?
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Several recommendations:
- Draw a picture of the equipment you need. Then encode the image.
- Hardware can only check 1 and 0. So your Z checks are problematic
- Use only tristats only in combination processes. Otherwise, there are many surprises and mistakes.
- Many FPGAs do not have internal tristats and therefore only support them for primary outputs.
Interpretation @ Jonathan Drole comment on "mixing combinational process with synchronous process". Think about it in terms of an exit.
Your synchronous processes ideally take the form:
SyncProc : process (Clk) is
begin
-- do not do logic here
if rising_edge(Clk) then
-- do synch stuff.
-- logic is ok in here
end if ;
-- do not do logic here
end process SyncProc ;
Ideally, your combination processes look like this:
CombProc : process (sig1, sig2, ...) is
begin
-- do logic stuff here
-- do not do clocks here
end process CombProc ;
Some tools will let you get away with more.
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I cannot be sure as the formatting of the messages is difficult to read. You seem to be assigning BD
inside and outside the rising_edge (clk) statement , which cannot be. BD
is either a register or not.
Do not mix combinational process with synchronous process. While the VHDL standard is not technically wrong, it is error prone like the one you have. Basically, a process sensitive to clk
should not be sensitive to any other signal other than an asynchronous reset.
Divide your process into one that is sane on n_OE
and DIR
, and the other on clk
. It will be clear that you are assigning BD
in both processes that translate to multiple drivers for the signal, which is usually wrong in synthesis.
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