Test bench for writing verilog output to a text file
I cannot get the correct output in the text file, but the simulation in modelsim is quite ok. But when writing to text file im getting XX for every input. maybe there is a syntax error or some other. if anyone can help plz write a test bench to write dout (output) of a flipflop (as an example) with each pin (output) displayed on a new line in a text file.
code:
module LFSR( clk,reset,out);
parameter width =4;
input clk,reset;
output [width-1:0] out ;
reg [width-1:0] lfsr;
integer r;
wire feedback = lfsr[width-1]^lfsr[width-2];
always @(posedge clk)
if (reset)
begin
lfsr <= 4'b1000;
end
else
begin
lfsr[0] <= feedback;
for(r=1;r<width;r=r+1)
lfsr[r]<=lfsr[r-1];
end
assign out=lfsr;
endmodule
Testbench:
module aaatest();
parameter width =4;
reg clk,reset;
wire [width-1:0] out;
reg [width-1:0] lfsr[13:0];
integer f,i;
initial
begin
f = $fopen("output.txt","w");
end
LFSR patt (clk,reset,out);
always #5 clk=~clk;
initial begin
clk=1; reset=1;
#10 reset=0;
# 140 $stop;
end
initial
begin
clk=1;
for (i = 0; i<14; i=i+1)
@(posedge clk)
lfsr[i]<= out;
end
initial begin
for (i = 0; i<14; i=i+1)
$fwrite(f,"%b\n",lfsr[i]);
end
initial begin
$display("clk out");
$monitor("%b,%b", clk, out);
end
initial
begin
$fclose(f);
end
endmodule
source to share
I would like you to think about these sections of code:
initial begin
f = $fopen("output.txt","w");
end
initial begin
for (i = 0; i<14; i=i+1)
$fwrite(f,"%b\n",lfsr[i]);
end
initial begin
$fclose(f);
end
When describing hardware, we have massive parallel modeling. All initials are meant to run at the same time, time 0.
If this works at all, since there is no guarantee that the file will be opened before you write it, you will write the file at zero time before you have yet to reset the logic that mimics.
Maybe something like below:
initial begin
f = $fopen("output.txt","w");
@(negedge reset); //Wait for reset to be released
@(posedge clk); //Wait for fisrt clock out of reset
for (i = 0; i<14; i=i+1) begin
$fwrite(f,"%b\n",lfsr[i]);
end
$fclose(f);
end
To follow Greg's suggestions, reset, released too early, considers something similar to:
initial begin
clk=0; reset=1; //Clock low at time zero
@(posedge clk);
@(posedge clk);
reset=0;
# 140 $stop;
end
Storing reset for two rising edges.
Updating with a working example
There are some strange things, you call $stop
(Not $finish
) after #140
but also try to loop 14 times, $ stop only does 4 loops.
Your test program consists of 2 initial begins
running in parallel, not one program running sequentially. You didn't have a delay in writing a text file, and you wrote a buffered version of lfsr, not the output of lfsr directly.
The following example correctly mimics and writes the text file you are looking for:
module aaatest();
parameter width =4;
reg clk,reset;
wire [width-1:0] out;
reg [width-1:0] lfsr[13:0];
integer f,i;
LFSR patt (clk,reset,out);
always #5 clk=~clk;
//Clock and reset release
initial begin
clk=0; reset=1; //Clock low at time zero
@(posedge clk);
@(posedge clk);
reset=0;
end
initial begin
f = $fopen("output.txt","w");
@(negedge reset); //Wait for reset to be released
@(posedge clk); //Wait for fisrt clock out of reset
for (i = 0; i<14; i=i+1) begin
@(posedge clk);
lfsr[i] <= out;
$display("LFSR %b", out);
$fwrite(f,"%b\n", out);
end
$fclose(f);
$finish;
end
endmodule
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