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What is fast LEA and slow LEA block in Inte CPU microarchitecture?

I saw the havewell microarchitecture from below mentioned link mentions that some pipelines can keep fast LEA and some can run slow LEA, what does fast LEA and slow LEA mean here? Related to LEA instruction? Search results are usually biased towards the LEA statement and do not lead to a direct answer.

http://www.realworldtech.com/haswell-cpu/4/

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Most of the dedicated ALUs only exist on a fraction of the working ports (with constant changes occurring from generation to generation), the CPU has to choose one of the possible ports according to the instruction (or rather, a micro-operation) executed. When several identical ports can do the same, it must try to do some balancing, and there may be other possible factors. The exact algorithm is, of course, never published.



In this case, however, LEA operations are divided into slow and fast, according to this link , slow due to the use of 3 LEA operands (base, index, offset). In fact, it also gives you a performance monitor to determine the number of such cases that you encounter.

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